A Network on Chip Simulator

Future integrated circuits that contain more than one billion transistors will allow much more complex designs than possible today. Unfortunately, there will be problems with clock distribution and on-chip communication delays. One approach to address these problems is to make a Network on Chip (NoC), that handles communication over the chip. Research in the area is being done at KTH, and a simulator is needed. This master thesis describes how a NoC simulator, capable of simulating various topologies, was implemented. The simulator was based on the OSI reference model, with the layers individually represented as exchangeable modules. A suitable model of execution and a hierarchic model of a NoC was designed. The result is a simulator that, in di erent aspects, resembles both network and microprocessor simulators. A case study of a real world DSP core mapped to a NoC, was performed with the simulator. A 2D mesh topology was used for all simulations.